/*
 * Copyright 2024 ywcai
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

`include "../core/defines.v"
`timescale 1ns/1ps

module ram(
	input   wire					clk,
	input   wire					rst_n,

	input   wire                    we_i,
	input   wire[`MemAddrBus]		addr_i,
	input   wire[`RegDataBus]		wr_data_i,
	input	wire[7:0]				strb_i,

	output  wire[`RegDataBus]		rd_data_o,
    output	wire[1:0]				errcode_o
	);

	reg[`RegDataBus]	_ram[`RAM_NUM-1:0];
	reg[`MemAddrBus]	rd_addr;
	integer				loop;

    initial begin
        for (loop = 0; loop < `RAM_NUM; loop = loop + 1) begin
            _ram[loop] = `XLEN'h0;
        end
    end

	always @(posedge clk) begin
		if (rst_n == `RESET_ENABLE) begin
			rd_addr <= `ZERO_ADDR;
		end else begin
			if (we_i == `ENABLE) begin
				_ram[addr_i[`ADDR_MSB:`ADDR_LSB]] <= wr_data_i;
			end
			rd_addr <= addr_i;
		end
	end

    assign rd_data_o = (rst_n == `RESET_ENABLE) ? `ZERO :
		_ram[rd_addr[`ADDR_MSB:`ADDR_LSB]];
    assign errcode_o = 2'b00;

endmodule
